Power consumption is a significant design and operational issue in many types of integrated circuits. For example, in deep-submicron technologies, high leakage power consumption is a major concern. A common technique for reducing power consumption in certain types of chips is body biasing. Body biasing solutions reduce the leakage power of a system by altering the bulk node potential (Vbulk) at the expense of operating frequency. The bulk node potential refers to the voltage at the bulk terminal of a semiconductor device. Certain types of metal-oxide semiconductors, such as field-effect transistors (FETs), comprise four terminals—a gate terminal, a drain terminal, a source terminal, and a bulk terminal. The gate terminal controls the opening and closing of a physical gate. The gate permits electrons to flow through or blocks their passage by creating or eliminating a channel between the source terminal and the drain terminal. Electrons flow from the source terminal towards the drain terminal if influenced by an applied voltage. The bulk terminal or node refers to the bulk of the semiconductor in which the gate, source and drain reside. The bulk terminal serves the purpose of biasing the transistor into operation.
Body biasing is a technique by which bulk terminals of the semiconductor devices are connected together, and the voltage at this “bulk node” is altered to reduce the leakage power of the chip. The bulk node voltage may be altered to produce back biasing or forward biasing. For example, when body biasing an n-type FET, back biasing refers to reducing the bulk node voltage below the source voltage (VSS). Back biasing may be used to reduce leakage power at the cost of decreased speed and performance of the transistors. Forward biasing refers to increasing the bulk node voltage above the source voltage. Forward biasing improves the speed and performance of the transistors at the cost of increased power leakage.
Currently, there are various adaptive body biasing (ABB) control schemes that are used to automatically adjust the bulk node voltage to minimize leakage power of a die without causing a functional failure. ABB control systems implement an autonomous closed-loop solution comprising process monitors, control circuitry, and voltage regulators. The process monitors estimate die conditions (e.g., process, voltage, and temperature (PVT) conditions). The control circuitry, which is added to the chip, determines whether to raise, lower, or maintain the bulk node voltage based on the PVT conditions. The voltage regulators serve the function of changing the bulk node voltage based on the control circuitry.
In one common ABB control scheme, the control circuitry comprises critical path replica (CPR) circuits that are added to the chip to replicate certain paths of electronic circuitry that are critical to the performance of the chip. A critical path may represent a particular circuit on the chip that is slower, due to any variety of reasons, such as circuit complexity. A circuit path that limits or otherwise affects the overall performance frequency of other circuit paths and/or or the chip itself may be considered a critical path. In this ABB control scheme, a copy of each critical path in the design is added to the chip. Each CPR includes a timing delay that provides the timing margin for the scheme. The body bias voltage is altered slowly in the design, and this increases the delay of the critical paths. Once the critical path delay approaches a timing failure (or maximum frequency), the paths in the monitor fail first due to the added timing margin. When a failure is detected in the critical path, the body bias is not scaled and is maintained at the current level. This technique ensures that the body bias is set at an optimal level without causing a timing failure.
In addition to CPR circuits, some ABB control schemes add extra logic (referred to as critical path detectors (CPD)) to each critical path in the design. In each CPR logic, a further timing delay is added for providing the timing margin. In this scheme, the body bias voltage is altered slowly and this increases the delay of the critical paths. When the critical path delay approaches a timing failure (or maximum frequency), the paths in the CPD fail first due to the added timing margin. Once a failure is detected in the CPD logic, the body bias is not scaled and is maintained at the current level. This technique also ensures that the body bias is set at an optimal level without causing a timing failure.
Existing ABB control schemes, however, have significant disadvantages. They require adding extra logic into critical paths of the chip, which increases the cost, complexity, and the development time of the design. They also rely on exciting each critical path during normal operation in order to control the bulk node voltage. Furthermore, the chip overhead is increased in proportion to the number of critical paths being monitored.
Despite the many advantages of existing ABB control schemes, there remains a need in the art for improved schemes that address one or more of these disadvantages.